六位元多工器結構模式

module top
wire [4:0]A,B,OUT;
wire SEL;
system_clock #40960 clock1(A[3]);
system_clock #20480 clock2(A[4]);
system_clock #10240 clock3(A[3]);
system_clock #5120 clock4(A[2]);
system_clock #2560 clock5(A[1]);
system_clock #1280 clock6(A[0]);
system_clock #640  clock7(B[5]);
system_clock #320  clock8(B[4]);
system_clock #160  clock9(B[3]);
system_clock #80  clock10(B[2]);
system_clock #40  clock11(B[1]);
system_clock #20  clock12(B[0]);
system_clock #10  clock13(SEL);
mux2  M1(OUT,A,B,SEL);
endmodule
/*一位元多工器  */
module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B)
or I4 (OUT, sel_a, sel_b);
endmodule
/*五位元多工器  */
module mux222(OUT, A, B, SEL);
output [4:0] OUT
input [5:0] A,B;
input SEL;
mux hi     (OUT[5],A[5],B[5], SEL);
mux middle1(OUT[4],A[4],B[4], SEL);
mux middle2(OUT[3],A[3],B[3], SEL);
mux middle3(OUT[2],A[2],B[2], SEL);
mux middle(OUT[1],A[1],B[1],SEL)
mux lo     (OUT[0],A[0],B[0], SEL)
endmodule
/*系統時脈  */
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop
endmodul