三位元多工器結構模式

module top
wire [2:0]A,B,OUT;
wire SEL;
system_clock #6400 clock1(A[0]);
system_clock #3200 clock2(A[1]);
system_clock #1600 clock3(A[2]);
system_clock #800  clock4(B[0]);
system_clock #400  clock5(B[1]);
system_clock #200  clock6(B[2]);
system_clock #100  clock7(SEL)
mux3  M1(OUT,A,B,SEL);
endmodule
/*一位元多工器  */
module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule
/*三位元多工器  */
module mux3(OUT, A, B, SEL)
output [2:0] OUT;
input [2:0] A,B;
input SEL;
mux hi    (OUT[2], A[2], B[2], SEL);
mux middle(OUT[1],A[1],B[1],SEL);
mux lo    (OUT[0], A[0], B[0], SEL);
endmodule
/*系統時脈  */
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop
endmodule