一位元加法器行為模式設計與測試

module test_adder1;

 reg a,b;
 reg carry_in ; 
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial 
  begin

   

    carry_in = 0; a = 0; b = 0; 
    # 100 if ( carry_in != 0 | sum !== 0) 
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1; 
    # 100 if ( carry_in != 0 | sum !== 1) 
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0; 
    # 100 if ( carry_in != 0 | sum !== 1) 
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 1; 
    # 100 if ( carry_in != 1 | sum !== 0) 
               $display(" 0+1+1=10 sum is WRONG!");
              else
               $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0; 
    # 100 if ( carry_in != 0 | sum !== 1) 
               $display(" 1+0+0=01 sum is WRONG!");
              else
               $display(" 1+0+0=01 sum is RIGHT!");
     carry_in = 1; a = 0; b = 1; 
    # 100 if ( carry_in != 1 | sum !== 0) 
               $display(" 1+0+1=10 sum is WRONG!");
              else
               $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0; 
    # 100 if ( carry_in != 1 | sum !== 0) 
               $display(" 1+1+0=10 sum is WRONG!");
              else
               $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1; 
    # 100 if ( carry_in != 1 | sum !== 1) 
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");

    $finish;
  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in); 
  assign carry_out = a&carry_in|a&b|b&carry_in; 
endmodule

六位元多工器結構模式

module top
wire [4:0]A,B,OUT;
wire SEL;
system_clock #40960 clock1(A[3]);
system_clock #20480 clock2(A[4]);
system_clock #10240 clock3(A[3]);
system_clock #5120 clock4(A[2]);
system_clock #2560 clock5(A[1]);
system_clock #1280 clock6(A[0]);
system_clock #640  clock7(B[5]);
system_clock #320  clock8(B[4]);
system_clock #160  clock9(B[3]);
system_clock #80  clock10(B[2]);
system_clock #40  clock11(B[1]);
system_clock #20  clock12(B[0]);
system_clock #10  clock13(SEL);
mux2  M1(OUT,A,B,SEL);
endmodule
/*一位元多工器  */
module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B)
or I4 (OUT, sel_a, sel_b);
endmodule
/*五位元多工器  */
module mux222(OUT, A, B, SEL);
output [4:0] OUT
input [5:0] A,B;
input SEL;
mux hi     (OUT[5],A[5],B[5], SEL);
mux middle1(OUT[4],A[4],B[4], SEL);
mux middle2(OUT[3],A[3],B[3], SEL);
mux middle3(OUT[2],A[2],B[2], SEL);
mux middle(OUT[1],A[1],B[1],SEL)
mux lo     (OUT[0],A[0],B[0], SEL)
endmodule
/*系統時脈  */
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop
endmodul

三位元多工器行為模式

module top
wire [2:0]A,B,OUT;
wire SEL;
system_clock #6400 clock1(A[1]);
system_clock #3200 clock2(A[0]);
system_clock #1600 clock3(A[2]);
system_clock #800 clock4(B[1]);
system_clock #400 clock5(B[0]);
system_clock #200 clock6(B[2]);
system_clock #100 clock7(SEL);
mux3  M1(OUT,A,B,SEL)
endmodule

module mux3(OUT, A, B, SEL);
 output OUT;
 input  [2:0] A,B;
 input   SEL;
 wire   [2:0] A, B;
 wire         SEL;
 reg    [1:0] OUT

  always @(A[0] or A[1] or A[2] or B[0] or B[1] or B[2] or SEL)
   begin
    OUT = (A[0] & SEL)|(B[0] & ~SEL );
    OUT = (A[1] & SEL)|(B[1] & ~SEL );
    OUT = (A[2] & SEL)|(B[2] & ~SEL );
   end
endmodule

/*宣告兩位元以上的，需要begin & end  */

/*系統時脈  */
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>7000)$stop
endmodule

三位元多工器結構模式

module top
wire [2:0]A,B,OUT;
wire SEL;
system_clock #6400 clock1(A[0]);
system_clock #3200 clock2(A[1]);
system_clock #1600 clock3(A[2]);
system_clock #800  clock4(B[0]);
system_clock #400  clock5(B[1]);
system_clock #200  clock6(B[2]);
system_clock #100  clock7(SEL)
mux3  M1(OUT,A,B,SEL);
endmodule
/*一位元多工器  */
module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule
/*三位元多工器  */
module mux3(OUT, A, B, SEL)
output [2:0] OUT;
input [2:0] A,B;
input SEL;
mux hi    (OUT[2], A[2], B[2], SEL);
mux middle(OUT[1],A[1],B[1],SEL);
mux lo    (OUT[0], A[0], B[0], SEL);
endmodule
/*系統時脈  */
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop
endmodule

二位元多工器行為模式設計

邏輯閘的設計

10/14二位元多工器

module top

wire [1:0]A,B,OUT;

wire SEL;

system_clock #200 clock1(A[1]);

system_clock #200 clock2(A[0]);

system_clock #100 clock3(B[1]);

system_clock #100 clock4(B[0]);

system_clock #400 clock5(SEL);

mux2  M1(OUT,A,B,SEL);

endmodule

/*一位元多工器  */

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL);

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

/*兩位元多工器  */

module mux2(OUT, A, B, SEL);

output [1:0] OUT;

input [1:0] A,B;

input SEL;

mux hi (OUT[1], A[1], B[1], SEL);

mux lo (OUT[0], A[0], B[0], SEL);

endmodule

/*系統時脈  */

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>1000)$stop

endmodule

10/7單一位元多工器

注意週期!!

新手入門

9/30學習內容
主要學會如何使用邏輯閘

module top;  module //xxxß將一個電路板命名為xxx//

wire A, B, OUT   //wire電路板的線//
system_clock #400 clock1(A);
system_clock #200 clock2(B);

and a1(OUT, A, B);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule